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NCP1578 Product Preview Synchronous Step-Down Controller with 50 mA Linear Regulator
The NCP1578 is a voltage mode synchronous step-down controller for high performance systems intended to be used in battery-powered systems. The NCP1578 includes a high efficiency PWM controller with adjustable output, and a 5 V/50 mA linear regulator. A pin is provided to enable or disable forced PWM mode of operation. An internal power good voltage monitor tracks the SMPS output. NCP1578 also features soft-start sequence, UVLO for linear regulator and switcher, overvoltage protection, overcurrent protection, and thermal shutdown. The IC is packaged in QFN20.
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QFN20 MN SUFFIX CASE 485E
MARKING DIAGRAM
20 1 N1578 ALYWG G N1578 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
* * * * * * * * * * * * * * * * * * *
Typical Applications
Network HUB, Switchers and Routers 3-Cell and 4-Cell Li-ion Battery-Powered Devices Personal Computer Peripherals Microprocessors Power Supply Embedded Controller DSP and Core Processor Supply for LCD Display
VBST TG SWN VCCP BG FPWM EN_LDO OCSET FOFF EN_SW LDO5 VBAT AGND NC FB PGND PGDLY PGOOD SS COMP
Fixed 5.0 V/50 mA Internal Linear Regulator Adjustable PWM Output Voltage 1.5% Accuracy 0.8 V Reference 4.5 V to 24 V Battery/Adaptor Voltage Range Selectable Force PWM Mode Lossless, Programmable High Side MOSFET's RDS(ON) Current Sensing Soft-start and Power-Up Sequencing Overvoltage Protection, Undervoltage Protection Programmable Delay Power Good Output Thermal Shutdown Housed in QFN20 This is a Pb-Free Device
PIN CONNECTIONS
ORDERING INFORMATION
Device NCP1578MNR2G Package QFN20 (Pb-Free) Shipping 4000/Tape & Reel
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
October, 2007 - Rev. P2
Publication Order Number: NCP1578/D
NCP1578
DETAILED BLOCK DIAGRAM
AGND AGND VREF - 35% + UVP OVP
THERMAL SHUTDOWN TSD OC FAULT INREGOUT CONTROL LOGIC
VREF
FB + -
OCSET
VREF + 15% FB VREF - 15% EN_LDO PGOOD
VBST + PGth SMPS PWM CONTROLLER TG SWN VCCP BG
PROGRAMMABLE DELAY PG_DLY AGND
OSC
PGND COMP FB
ADAPTIVE RAMP REFERENCE
VREF
FOFF
FPWM VBAT SS EN_SW SOFT START CONTROL VCC UVLO CONTROL 5V LDO
VCC LDO5
Figure 1. Detailed Block Diagram
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NCP1578
TYPICAL APPLICATION CIRCUITS
VIN (6 ~ 24 V)
VOUT
VCCP
VOUT_GND BG PU
VBST
FPWM
FPWM EN_LDO OCSET FOFF EN_SW
SWN
TG
1
PGND PGDLY PGOOD SS COMP PGOOD
EN_SW LDO5 AGND VBAT NC FB VIN (4.5 ~ 24 V)
Figure 2. Single Supply VBAT Configuration
Ext +5V
VOUT
VCCP
VOUT_GND BG PU
VBST
FPWM
FPWM EN_LDO OCSET FOFF
SWN
TG
1
PGND PGDLY PGOOD SS COMP PGOOD
EN_SW
EN_SW
LDO5
AGND 3
Figure 3. External 5 V and VIN Configuration
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VBAT
NC FB
NCP1578
PIN FUNCTION DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Symbol FPWM EN_LDO OCSET FOFF EN_SW LDO5 VBAT AGND NC FB COMP SS PGOOD PGDLY PGND BG VCCP SWN TG VBST THPAD Description FPWM or Power Saving Control. Logic high enables force PWM. Logic low enables power saving operation. LDO enable input. The 5 V LDO is enabled if EN_LDO is high and disabled if it is low. This pin can sustain voltage as high as VBAT. Input pin for over current threshold setting for high side gate driver. Also it is for the internal ramp gen erator to implement the voltage feed forward rejection to the input voltage variation Fault OFF. If it pulls to high, it disables the features of OCP, UVLO and OVP. Normally it should be tied to ground. This pin is internally pulled down. PWM controller's enable input. The switching controller is enabled if EN_SW is high and disabled if EN is low. 5.0 V linear regulator output. Battery/adaptor voltage input. Analog ground. Not connected Feedback input from controller's output voltage. Error amplifier output pin. Soft-start (for switcher) capacitor connection to ground. Power good signal open drain output. High impedance (open drain) if power is good (in regulation). Low impedance if power is not good. Power good delay capacitor connection to ground. Power ground. Gate driver output for low-side N-Channel power FET. Power Input voltage pin. Inductor driven node of the SMPS, the return for high-side gate driver, and also serve as the lower supply rail of the high-side gate driver of the SMPS. Gate driver output for high-side N-Channel power FET. Positive supply of high-side gate driver of the SMPS. Connect boost capacitor between this pin and switching node SWN of the SMPS. Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC.
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NCP1578
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Voltage to AGND (VCC internally connects to LDO5) High-side Gate Drive Supply: BST to SWN High-side FET Gate Drive Voltage: TG to SWN Input / Output Pins (except EN_LDO and OCSET) to AGND VBAT Input to AGND EN_LDO Input to AGND OCSET Input to AGND Switch Node SWN PGND Thermal Characteristics QFN20 Plastic Package Thermal Resistance Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VLDO5 VBST-VSWN, VTG-VSWN VIO VVBAT VEN_LDO VOCSET VSWN VGND RJA Value -0.3, 6.0 -0.3, 6.0 -0.3, 6.0 -0.3, 27 -0.3, 27 -4 (< 100 ns), -0.3 (dc), 32 -0.3, 0.3 47 Unit V V V V V V V _C/W
TJ TA Tstg MSL
-40 to +150 -40 to +85 -55 to +150 1
_C _C _C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device is ESD sensitive. Use standard ESD precautions when handling This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115 for all pins. 2. Latch-up Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
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NCP1578
ELECTRICAL CHARACTERISTICS
(VBAT = 12 V, LDO5 = VCCP = 5 V, TA = -40 to 85C, for min/max values unless otherwise noted. Typical values are at TA = 25_C.) Characteristic SUPPLY SECTION Input Voltage VBAT Operating Supply Current VBAT IBAT Single Supply Configuration, See Figure 2 Ext +5 V and VIN Configuration, See Figure 3 LDO5 & SMPS are Enabled, See Figure 2 TG and BG are 3 nF Capacitor Load VBAT = 12 V VBAT = LDO5 See Figure 3 TG and BG are 3 nF Capacitor Load VBAT = 5 V VBAT Shutdown Current UNDERVOLTAGE MONITOR LDO5 UVLO Lower Threshold LDO5 Undervoltage Lockout Hysteresis LINEAR REGULATOR LDO5 Input Voltage Range LDO5 Output Voltage LDO5 Maximum Output Current SMPS CONTROLLERS FB Feedback Voltage, Control Loop in Regulation Operating Frequency Ramp Amplitude Ramp Amplitude to VIN Ratio Minimum Duty Cycle Maximum Duty Cycle Voltage Error Amplifier DC Gain Error Amplifier Unity Gain Bandwidth Voltage Error Amplifier Slew Rate OCSET Pin Current Sink OCSET Pin Current Sink Temperature Coefficient TG Gate Driver Pull-High Resistance TG Gate Driver Pull-Low Resistance BG Gate Driver Pull-High Resistance BG Gate Driver Pull-Low Resistance Soft-start Current PGDLY Delay Current PGDLY Threshold VFB FSW VRAMP DVRAMP/DVIN Dmin Dmax Gain Ft SR IOC TCIOC RH_TG RL_TG RH_BG RL_BG Iss IPG_DLY VthPG_DLY VBST - VSWN = 5 V, VTG - VSWN = 4 V VBST - VSWN = 5 V, VTG - VSWN = 1 V VCCP = 5 V, VBG = 4 V VCCP = 5 V, VBG = 1 V EN_SW = 5.0 V; Vss = 0 V EN_SW = 5.0 V, VPG_DLY = 0 V 2.8 1.4 VOCSET = 4.5 V to 24 V (Note 3) COMP to GND = 100 pF, 1.0 W in Series (Note 3) (Note 3) OCSET = 4.0 V VOCSET = 12 V (Note 3) VOCSET = 4.5 V to 24 V (Note 3) TA = 25C TA = -40 to 85C 0.792 0.788 270 90 34 0.8 0.8 300 1.02 83 70 2 3.0 40 3200 1.5 1.5 1.5 0.9 4.0 2.0 1.25 4.0 4.0 4.0 3.0 5.2 2.6 0.808 0.812 330 0 50 V kHz V mV/V % % dB MHz V/is mA ppm/C W W W W mA mA V LDO5_IN LDO5 ILDO5_MAX VBAT = LDO5 for 5 V Configuration See Figure 3 VBAT = 6 V to 24 V, EN_LDO > 1.4 V, ILDO5 = 0 to 50 mA VBAT = 6 V to 24 V, EN_LDO > 1.4 V 4.5 4.85 50 5.0 5.0 5.5 5.15 V V mA VLDO5UVVLDO5UVHYS Falling Edge 4.1 330 V mV IBATSD VBAT = 6 V to 24 V, EN_LDO = 0 V, EN_SW = 0 V 6.0 4.5 24 V mA 2 3 3 mA Symbol Test Conditions Min Typ Max Unit
-
10
30
mA
3. Guaranteed by design, not tested in production.
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NCP1578
ELECTRICAL CHARACTERISTICS
(VBAT = 12 V, LDO5 = VCCP = 5 V, TA = -40 to 85C, for min/max values unless otherwise noted. Typical values are at TA = 25_C.) Characteristic FAULT DETECTION Overvoltage Trip Threshold Undervoltage Trip Threshold PGOOD Lower Threshold PGOOD Pin ON Resistance PGOOD Pin Leakage Current Thermal Shutdown Trip Point Thermal Shutdown Hysteresis LOGIC INPUT LEAKAGE EN_LDO Threshold High EN_LDO Threshold Low EN_LDO Input Current VENLDO_H VENLDO_L IINLDO_EN1 IINLDO_EN2 EN_SW Threshold High EN_SW Threshold Low EN_SW Input Current FPWM Threshold High FPWM Threshold Low FPWM Input Current FOFF Threshold High FOFF Threshold Low FOFF Input Current VENSW_H VENSW_L IINSW_EN FPWM_H FPWM_L IIN_FPWM FOFF_H FOFF_L IIN_FOFF LDO ON LDO OFF EN_LDO = 5.0 V EN_LDO = 24.0 V SMPS ON SMPS OFF EN_SW = 5.0 V Set as Force PWM Mode Set as Power Saving Mode FPWM = 5.0 V Disable OCP, UVLO & OVP OCP, UVLO & OVP are in function FOFF = 5.0 V (Internal Pull Down by 1 MW) 1.4 1.4 1.4 1.4 5.0 0.5 1 10 0.6 1.0 0.6 1.0 0.6 V V mA mA V V mA V V mA V V mA OVPth UVPth VPGPGOOD_R PGOOD_LK TSD TSDHYS (Note 3) (Note 3) With Respect to FB Voltage With Respect to FB Voltage With Respect to FB Voltage I_PGOOD = 5.0 mA -20 110 65 70 150 25 120 -10 1.0 % % % W mA C C Symbol Test Conditions Min Typ Max Unit
3. Guaranteed by design, not tested in production.
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NCP1578
TYPICAL OPERATING CHARACTERISTICS
20 VBAT, SHUTDOWN CURRENT (mA) LDO5 OUTPUT VOLTAGE (V) Vin = 24 V 15 5.06 Vin = 24 V, 0 mA
5.04
Vin = 24 V, 50 mA
5.02
10
5.00 Vin = 6 V, 0 mA 4.98 Vin = 6 V, 50 mA
5 Vin = 6.0 V 0 -40 -15 10 35 60 TA, AMBIENT TEMPERATURE (C) 85
4.96 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
Figure 4. VBAT Shutdown Current vs. Ambient Temperature
0.90 SWITCHING FREQUENCY (kHz) VFB, FEEDBACK VOLTAGE (V) 320
Figure 5. LDO5 Output Voltage vs. Ambient Temperature
0.85
310
0.80
300
0.75
290
0.70 -40
-15
10
35
60
85
280 -40
-15
10
35
60
85
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 6. VFB Feed Back Voltage vs. Ambient Temperature
44 43.5 IOC CURRENT (mA) 43 42.5 42 41.5 41 -40 ISS, SOFT-START CURRENT (mA) 4.5
Figure 7. Switching Frequency vs. Ambient Temperature
4.4
4.3
4.2
4.1
-15
10
35
60
85
4.0 -40
-15
10
35
60
85
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 8. IOC Current vs Ambient Temperature
Figure 9. Soft-Start Current vs. Ambient Temperature
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NCP1578
TYPICAL OPERATING CHARACTERISTICS
2.5 PGOOD, DELAY THRESHOLD (V) PGOOD, DELAY CURRENT (mA) 1.25
2.3
1.24
2.1
1.23
1.9
1.22
1.7
1.21
1.5 -40
-15
10
35
60
85
1.20 -40
-15
10
35
60
85
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 10. PGOOD Delay Current vs. Ambient Temperature
116 UNDERVOLTAGE THRESHOLD (%) OVERCURRENT THRESHOLD (%) 66
Figure 11. PGOOD Delay Threshold vs. Ambient Temperature
115.8
65.5
115.6
65
115.4
115.2
64.5
115 -40
-15
10
35
60
85
64 -40
-15
10
35
60
85
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 12. Overcurrent Threshold vs. Ambient Temperature
-14.5 PGOOD LOWER THRESHOLD (%) EN_LDO LEAKAGE @ 24 V (mA) 5.0
Figure 13. Undervoltage Threshold vs. Ambient Temperature
-14.8
4.5
-15
4.0
-15.3
3.5
-15.5 -40
-15
10
35
60
85
3.0 -40
-15
10
35
60
85
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 14. PGOOD Lower Threshold vs. Ambient Temperature
Figure 15. EN_LDO Leakage Current vs. Ambient Temperature
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NCP1578
TYPICAL OPERATING CHARACTERISTICS
3.350 3.350
Vo, OUTPUT VOLTAGE (V)
Vo, OUTPUT VOLTAGE (V)
3.325 Io = 0 A 3.300 Io = 5 A 3.275
3.325 Vo = 24 V 3.300 Vo = 6 V 3.275
3.250
5
10
15 Vin, INPUT VOLTAGE (V)
20
25
3.250 0.5
1.5
2.5
3.5
4.5
Io, OUTPUT CURRENT (A)
Figure 16. Vo Output Voltage vs. Input Voltage
Figure 17. Vo Output Voltage vs. Output Current
100
100 Vin = 6 V 90 EFFICIENCY (%) Vin = 12 V Vin = 24 V 80 Vo = 3.3 V FSW = 300 kHz TA = 25C EFFICIENCY (%)
Vin = 6 V 90 Vin = 12 V Vin = 24 V 80 VBAT = +5.0 V Vo = 3.3 V FSW = 300 kHz TA = 25C With Power Saving Without Power Saving 1 Io, OUTPUT CURRENT (A) 10
70
70
60 With Power Saving Without Power Saving 1 Io, OUTPUT CURRENT (A) 10
60
50 0.1
50 0.1
Figure 18. Vo Efficiency vs. Output Current (Single Supply)
Figure 19. Vo Efficiency vs. Output Current (Separate Supply)
Figure 20. Power Up Sequence
Figure 21. Power Down Sequence
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NCP1578
TYPICAL OPERATING CHARACTERISTICS
Figure 22. Switcher Operation - CCM Mode
Figure 23. Switcher Operation - DCM Mode
Figure 24. Switcher Operation - Pulse SkippingMode (PSM)
Figure 25. Switcher Operation - PSM Zoom-In
Figure 26. Load Transient - Load Step Up
Figure 27. Load Transient - Load Release
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NCP1578
TYPICAL OPERATING CHARACTERISTICS
Figure 28. Vout OCP by Short Circuit to Ground
Figure 29. Vout OCP by Steady Iout Increases
Figure 30. Undervoltage Protection
Figure 31. Overvoltage Protection
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NCP1578
DETAILED OPERATING DESCRIPTION
General
The NCP1578 synchronous step-down power controller contains a PWM controller and a 5 V/50 mA linear regulator for wide battery/adaptor voltage range applications The NCP1578 includes power good voltage monitor, soft-start, over current protection, undervoltage protection, overvoltage protection, LDO5 UVLO and thermal shutdown. The NCP1578 allows for improved efficiency at light loads by allowing the synchronous MOSFET to turn off automatically making this device a ideal for battery operated systems. The IC is packaged in QFN20.
Control Logic
For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a Schottky diode rectifier. Adaptive nonoverlap timing control of the complementary gate drive output signals is provided to reduce large shoot-through current that degrades efficiency. When the forced PWM is disabled, the low-side MOSFET is allowed to turn off after the detection of negative inductor current.
Overcurrent Protection of SMPS Controllers
The LDO5 is enabled when EN_LDO is high. The PWM controller is enabled when EN_SW is high. The internal Vref is activated whenever the output of LDO5 rises above the UVLO threshold of 65% of VFB volts, power-on reset occurs which resets all the protection faults. The device's control logic is powered by LDO5 internally. Once Vref reaches its regulation voltage, an internal signal will wake up the supply undervoltage monitor which will assert a "GOOD" condition if LDO5 voltage is within certain preset levels.
Linear Regulator
The 5 V linear regulator can supply total 50 mA current for both internal and external loads. It can be enabled or disabled independently by the control pin EN_LDO. When EN_LDO = 1, the UVLO voltage is set as 4.5 V with hystersis 330 mV typical. It is recommended to bypass LDO5 output with 1 mF (min) ceramic capacitors.
Switching Controller
An external resistor connected between the input voltage and OCSET sets the current limit for the high-side switch. An internal 40 mA current sink (IOC) at OCSET pin establishes a voltage drop across this resistor and develops a voltage at input and is compared to the voltage at SWN pin when the high-side gate drive is high after a fixed period of blanking time (X150 ns) to avoid false current limit triggering. When the voltage at SWN is lower than that at the input for 16 consecutive internal clock cycles, an over current condition occurs. Those 16 consecutive cycles will be operating as cycle by cycle condition in the way such that for each cycle, TG is OFF once the inductor current hits the preset threshold value. The SMPS output will be latched off after those 16 cycles to protect against a short-to-ground condition on SWN or OUT. The IC will be reset once LDO5 or EN_SW is cycled.
Output Voltages Sensing
The controller directly drives two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency with input voltage feedforward PWM. The part is compensated externally. The switching frequency is fixed at 300 kHz 10%. The SMPS output voltage is divided down via resistor network and fed back to the inverting input of an internal error amplifier through FB pin to close the loop at Vout. This amplifier compares the feedback voltage with an internal Vref to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TG and BG pins. External inductor and capacitor filter the output waveform. The SMPS output voltage ramps up at a pre-defined soft-start rate when the EN_SW pin goes HIGH from LOW after Vref is ready. Input voltage feedforward is implemented to the RAMP signal generation to reject the effect of wide input voltage variation. With input voltage feedforward, the amplitude of the RAMP is proportional to the input voltage.
The SMPS output voltage is sensed across the FB and AGND pins. FB should be connected through a feedback resistor divider to the output voltage point of regulation. The AGND should be connected directly through a sense trace to the remote ground sense point which is usually the ground of local bypass capacitor for load.
Supply Voltage Under-Voltage Monitor
The IC continuously monitors LDO5 output pin. The IC will shutdown if the voltage is below 4.5 V.
Thermal Shutdown
The IC will shutdown if the die temperature exceeds 150_C. The IC restarts operation only after the junction temperature drops below 125_C.
Power Good
The PGOOD is an open-drain output of a comparator which continuously monitors SMPS output voltage. The Power Good time delay can be programmable by connecting an external capacitor. The PGOOD is true (high impedance) when the FB pin is within $15% of the preset nominal regulation voltage. The PGOOD is false (pulled low) when FB rises above 15% or falls below 15% the nominal regulation point. PGOOD pin also pulls low when protection fault occurs (OVP, UVP, OTP, and UVLO), or
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NCP1578
SMPS is disabled by EN_SW. Note that the PGOOD pin is valid providing LDO5 is high enough to maintain the internal logic state.
Overvoltage Protection
Cycling EN_SW or LDO5 can reset the undervoltage fault latch and restart the controller.
Soft-Start
When SMPS output voltage is above 115% (typ) the preset nominal regulation voltage for 16 consecutive internal clock cycles, the SMPS output will be latch off and it can be restarted by toggling EN_SW or LDO5.
Undervoltage Protection
When SMPS output falls below 65% (typ) of the nominal regulation voltage for 16 consecutive internal clock cycles, the undervoltage fault is set, the SMPS is latched off.
OPERATION TABLE 1 (Single Supply VBAT Configuration)
Input Condition FPWM X X High Low EN_LDO Low High High High EN_SW X Low High High
The switcher VOUT soft-start feature is incorporated in the device to prevent surge current from power supply and output voltage overshot during power up. When EN_SW, LDO5 rises above their respective upper threshold voltages, the external soft start capacitor Css is charged by a constant current source Iss. When the soft-start voltage reaches the Vref voltage, the soft start process is finished. The soft-start time Tss can be programmed by the soft-start capacitor according to the following equation: Tss [ (0.8 x Css) / Iss.
Operating Condition SMPS Off Off On (FPWM) On (DCM or Pulse Skipping) LDO5 Off On On On
Output Condition PGOOD H-Z Low H-Z H-Z
OPERATION TABLE 2 (External +5 V and VIN Configuration (Note 4))
Input Condition FPWM X High Low EN_LDO (Note 5) Low Low Low EN_SW Low High High Operating Condition SMPS Off On (FPWM) On (DCM or pulse skipping) Output Condition PGOOD Low H-Z H-Z
4. External +5 V is connecting to VBAT and LDO5 pin. 5. For this configuration, it is recommended to pull EN_LDO to GND at any time.
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NCP1578
TIMING DIAGRAMS
VBAT
EN_LDO
LDO5
EN_SW SMPS VOUT Vout Drop Rate Depends on Output Loading
PGDLY
PGOOD VBAT > 6 V for LDO5 Ready LDO5 Soft-Start PGOOD is Undermined SMPS Soft-Start SMPS In PGOOD Delay PGOOD Goes Low EN_SW Should Be Regulation and Goes High when LDO5 Goes UVLO when LDO5 is too Low Ready when LDO5 is Threshold to Maintain Logic Level High Enough to LDO5 in Regulation Maintain Logic Level
Figure 32. Single VBAT Configuration (SMPS Disabled by EN_LDO)
VBAT
EN_LDO
LDO5
EN_SW SMPS VOUT Vout Drop Rate Depends on Output Loading
PGDLY
PGOOD VBAT > 6 V for LDO5 Ready SMPS Soft-Start SMPS In LDO5 Soft-Start EN_SW Should Be Regulation Ready when LDO5 is LDO5 in Regulation High Enough to Maintain Logic Level PGOOD Delay and Goes High PGOOD Goes Low whenever EN_SW Goes Low
Figure 33. Single VBAT Configuration (SMPS Disabled by EN_SW)
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NCP1578
TIMING DIAGRAMS (Continuous)
VBAT
VIN
LDO5
EN_SW SMPS VOUT Vout Drop Rate Depends on Output Loading
PGDLY
PGOOD LDO5 > 4.5 V to Enable IC EN_SW Goes High SMPS In Regulation PGOOD Delay and Goes High PGOOD Goes Low Whenever EN_SW Goes Low
Figure 34. External 5 V (Connect to VBAT and LDO5) and Vin Configuration
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NCP1578
GENERAL APPLICATION INFORMATION
Introduction
Figure 35 depicts the general control blocks of voltage mode control loop for a synchronous-rectified buck converter. The voltage output Vout is regulated to a reference level which is basically governed by the following formula
V out + 1 ) R1 R2 V FB
(eq. 1)
of the error amplifier is used to provide pulse-width modulated (PWM) wave.
Loop Compensation
In order to provide proper regulation, the error amplifier is compared with the internal reference voltage and the output
Since NCP1578 is a voltage mode PWM controller with LC output filter, type III compensation network is recommended to provide the good closed loop bandwidth and phase boot with stability under any circumstances. The purpose of compensation is to obtain a stable close loop system with the highest possible bandwidth. In another word, we need to obtain a "fast and stable" system.
VIN
NCP1578 Modulator CIN Q1 TG VOUT PWM Logic Gate Driver & Ramp Generator BG SWN Q2 L DCR ESR COUT PGND Output Filter
COMP Vref Error Amp A FB C2 R3 C3 C1 R4
R1
Compensation Network
R2
Figure 35. Buck Converter with Modulator, Output Filter and Compensation Network Equations Involved in Compensation Network F P2 + 1 R4 (2nd Pole)
(eq. 7)
The following equations are provided as general guidelines for defining the positions of poles and zeros of the compensation network.
Output Filter Break Frequency F LC + 1 2p L C out 1 ESR (ESR Zero)
(eq. 3)
2p
C3
Guidelines for selecting compensation component
(LC Double Pole)
(eq. 2)
F ESR +
2p
C out
Compensation Network Break Frequency F Z1 + F P1 + 2p 1 R3 1 2p R3
C1 C2 C1)C2
C2
(1st Zero) (1st Pole)
(eq. 4)
(eq. 5)
F Z2 +
2p
1 (R1 ) R4)
C3
(2nd Zero) (eq. 6)
1. Select a value of R1 between 2 kW and 5 kW 2. Target for close loop bandwidth should be less than 50% of switching frequency 3. Place 1st zero at 50% of filter double pole. 4. Place 1st pole at ESR zero 5. Place 2nd zero at filter double pole 6. Place 2nd pole at half the switching frequency. Figure 36 shows an asymptotic plot of the converter gain against frequency. It gives the general trend of how system and its individual components behave. Actually, the Modulator and Filter Gain has a high peak due to the high Q factor of the output filter. The Open Loop Error Amplifier Gain bounds the Compensation Gain. The Converter Gain is constructed on the graph by summing up the Modulator and Filter Gain (in dB) and the Compensation Gain (in dB). The Compensation Gain uses the external impedance network (R1, R4, C3, C1, C2, R3 at Figure 35) to provide a
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NCP1578
stable and high bandwidth overall loop. Worst case component variation should be considered when selecting the components of impedance network such that the control loop phase margin should be greater than 45.
Open Loop Error Amp Gain
FZ1 = 0.5 FLC
FZ2 = FLC FP1 = FESR GAIN (dB) Converter Gain
FP2 = 0.5 FS
0dB
FLC Compensation Gain FESR Modulator & Filter Gain FREQUENCY
Figure 36. Bode Plot of the Converter Gain Input Capacitor Selection
It is used to minimize the input voltage ripple from the power supply source. The input capacitors should be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The PCB trace style should be in form of short and wide ones. The voltage rating and the RMS current rating are the important parameters for the bulk input capacitor. In typical application, the bulk capacitor should be selected such that the voltage and current ratings must above the maximum input voltage and largest RMS current required by system. As a safety guideline, the capacitor voltage rating should be at least 1.5 times greater than the maximum input voltage. And the RMS current rating requirement is approximately half of the DC load current. The required input capacitor RMS ripple current rating may be estimated by the following equation:I Cin(RMS) w I out V out V in(min) * V out V in(min)
2
capacitors should be used for switching regulator applications. For steady state ripple, both ESR and capacitance of the output capacitor contribute output ripple voltage. Normally, ESR is the dominant factor for output ripple voltage. The output ripple voltage DVo can be estimated by the following equation:
DV o + DI L ESR ) DI L 8 C out FS
(eq. 9)
and
DI L + (V in * V o) L FS Vo V in
(eq. 10)
(eq. 8)
Ceramic capacitor is the good choice of the input capacitor for notebook application due to its low ESR and good ripple current rating and high voltage rating. Aluminum electrolytic capacitors are also good choice. They are relatively low cost but they should be used in parallel connection to lower the ESR which is intrinsically high compared with ceramic capacitors.
Output Capacitor Selection
The output capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. So, only specialized low-ESR
DVo = DIL X ESR if Cout is large enough. Where: DIL = Inductor ripple current ESR = Effective Series Resistance of the output capacitor L = Inductance Cout = Output capacitance FS = Switching frequency Vin = Input Voltage Vo = Regulated output voltage From the above equations, it can be seen that the output ripple voltage can be reduced by either using the inductor with larger inductance or the output capacitor with smaller ESR value. In general rule of thumb, the inductor ripple current is typically 30% of the maximum load current and the ripple voltage is typically 2% of the output voltage. The output capacitor also plays an important role in response of load step up or release transients. The voltage
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undershoot DV- due to load step up DI can be estimated by the following equation:
DV * + DI ESR ) DI C out I*
Vo V
in
FS
(eq. 11)
and the voltage overshoot DV+ due to load release can be estimated by the following equation:
L DV ) + Io )
DI
2 L
It is because the switching on time of lower side MOSFET is longer than that of high side MOSFET especially at the high Vin and low Vo case. For practical application, high side MOSFET and low side MOSFET with RDSON about 7.0 mW and 5.0 mW respectively can achieve good efficiency. In order to have better immunity to low side MOSFET false switching on due to high dV/dt switching slew rate of the high side MOSFET, the low side MOSFET should be selected such that the ratio QGD/QGS should be low enough.
Overcurrent Protection Component Selection
2
) C out
V2 o
C out
* V OUT
(eq. 12)
The overcurrent protection will trip when a peak inductor current hit the ILIM which is determined by the equation:IsubsLIM + R OC I OC
(eq. 14)
Where: IO = Load current step Other parameters for selection of output capacitor are the voltage rating and ripple current rating. In general, the voltage rating should be at least 1.25 times the output voltage and the RMS ripple current rating should be greater then the inductor ripple current.
Output Inductor Selection
R DS(on)_HS
Basically, a physical inductor can be simply modeled as two components: an ideal inductance L and an ideal resistor DCR. The value of L determines the output ripple voltage, inductor ripple current and performance of load transients. And DCR contributes the system loss. Hence, the higher the DCR, the lower the efficiency of the system will be. In general, the typical inductor ripple current is 30% of the maximum load current. So based on this criteria, by simple rearrangement of Equation 10, the required inductance can be estimated as follow:Lw V in * V o 0.3 I O(max) Vo V in FS
(eq. 13)
Where: ROC = Resistor across OCSET pin and Vin IOC = Constant current flowing into the OCSET pin RDS(on)_HS = On resistance of the high side MOSFET Since IOC is varying with device to device and high side MOSFET's RDS(on) varies with temperature, so in order to prevent from mis-triggering the over current protection in normal operating condition, ROC should be determined based on the following corner conditions:1. The minimum IOC value from the electrical table. 2. The maximum high side MOSFET's RDS(on) used at the highest junction temperature. 3. Estimate ILIM such that ILIM > Io_max + DIL/2 where Io_max = Maximum output current rating, DIL = Inductor ripple current. In addition, a decoupling capacitor Coc should be added in parallel with ROC for noise filtering purpose.
PCB Layout Guidelines
Where: IO(max) = Maximum load current In addition, The DC current rating of the inductor should be about 1.2 times of the peak inductor current at maximum output load current and in order to achieve the good system efficiency, DCR should be minimized. In general, inductor with about 2 mW to 3 mW per mH should be used. In some cases, larger inductor value can be selected to achieve higher efficiency as long as it still meets the required voltage overshoot at load release and inductor DC current rating.
MOSFET Selection
For selection of MOSFET, gate drive voltage (VGS), ON-Resistance (RDSON), gate input capacitance (CGS) and gate charges (QG, QGD and QGS) are the key parameters to be considered. For ON-resistance, in consideration of efficiency and power dissipation, it should be the lower the better. In general, for the buck converter, the RDSON of low side MOSFET is usually lower than that of high side MOSFET.
The following items should be considered when preparing PCB layout: 1. All high current traces should be kept as short and wide as possible to reduce power loss. For example the input voltage terminal to the drain of high-side MOSFET, trace from inductor to the output terminal, etc. Power handling and heat sinking capability of power traces can be improved by multiple trace routing at different layer and join them together with multiple vias. 2. Power components which include the input capacitor, MOSFETs, inductor and output capacitor must be placed close together to minimize the current loop. 3. The thermal pad of the QFN20 package should be connected to the ground planes for providing good heat dissipation. It is recommended to use PCB with 1 oz or 2 oz copper foil. The thermal pad can
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NCP1578
be connected to either PGND or AGND but not on the both. 4. The ground terminals of input and output capacitors, and the low-side MOSFET's source pin should be connected to PGND ground plane through (if necessary) multiple vias. 5. Noise sensitive traces such as traces of FB, COMP and OCSET should be placed in order to prevent from interference of high voltage switching signal traces like SWN, VBST, TG and BG. 6. The feedback resistor divider should be placed as close as possible to FB pin. The output voltage sensing signal should be come up from the separated noise free signal trace. 7. To minimize the effect of parasitic impedance, traces between gate drivers to MOSFET's gates should be as shortest as possible.
VBAT Cin1 10uF Cin2 0.1uF
M1
NTMS7N03R2 L1 2.2uH Dbst MBR0530T1 Cbst 0.1uF Cvccp 1uF M2 Co2 Co1 180uF 180uF Co3 1uF D1 MBRM120L VO 3.3V, 5A
NTMS7N03R2
VCCP 17
VBST
SWN
20 FPWM FPWM Ren_ldo 100k Roc 4.7k Coc 10nF EN_SW EN_LDO 1 2
19
18
BG 16 15 14 PGND PGDLY PGOOD Css 82nF SS COMP Ccmp1 680pF Ccmp2 2.7nF AGND PGND Cpgdly 18nF 13 12 11
TG
U1 OCSET FOFF EN_SW 3 4 5 NCP1578NMR2 PGOOD
6 LDO5
7 VBAT
8 AGND
9 NC
10 FB
Rcmp 2.7k Rfb1 100 Cfb
Cvbat 10nF Rfb2a 5.6k Rldo 10 Cldo 1uF 1uF
Rfb3 1.8k
Figure 37. Typical Application Schematic Diagram
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BILL OF MATERIAL (BOM) FOR THE TYPICAL APPLICATION SCHEMATIC
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Qty 1 2 1 1 1 2 1 4 2 1 1 1 1 2 1 1 1 1 1 1 1 Designator U1 M1, M2 D1 Dbst L1 Co1, Co2 Cin1 Co3, Cvbat, Cldo, Cvccp Cin2, Cbst Cpgdly Css Ccmp1 Ccmp2 Cfb, Coc Rcmp Rfb1 Rfb2a Rfb3 Rldo Ren_ldo Roc Part Description NCP1578 Buck Controller NTMS7N03R2 MOSFET N-Ch 7A, 30V, 23mW @ 4.5V MBRM120L Schottky Diode 1A, 20V, POWERMITE MBR0530T1 Schottky Diode 0.5A, VF=0.375V @ 0.1A, SOD-123 FDA1055-2R2M 2.2uH, 4.8mW max SP-CAP, 180uF, 6.3V, ESR=10mW SIZE-D Ceramic Capacitor 10uF/25V, 2512 Ceramic Capacitor 1uF/10V, 0805 Ceramic Capacitor 0.1uF/25V, 0603 Ceramic Capacitor 18nF/50V, 0603 Ceramic Capacitor 82nF/50V, 0603 Ceramic Capacitor 680pF/50V, 0603 Ceramic Capacitor 2.7nF/50V, 0603 Ceramic Capacitor 10nF/50V, 0603 Resistor 2.7kW, 0603 Resistor 100W, 0603 Resistor 5.6kW, 0603 Resistor 1.8kW, 0603 Resistor 10W, 0603 Resistor 100kW, 0603 Resistor 4.7kW, 0603 Vendor ON Semicondutor ON Semicondutor ON Semicondutor ON Semicondutor TOKO Panasonic
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PACKAGE DIMENSIONS
20 PIN QFN, 4x4 CASE 485E-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 4.00 BSC 4.00 BSC 0.80 1.00 0.23 0.35 2.75 2.85 2.75 2.85 0.50 BSC 1.38 1.43 0.20 REF 0.00 0.05 0.35 0.45 2.00 BSC 2.00 BSC 1.38 1.43 0.60 0.80 INCHES MIN MAX 0.157 BSC 0.157 BSC 0.031 0.039 0.009 0.014 0.108 0.112 0.108 0.112 0.020 BSC 0.054 0.056 0.008 REF 0.000 0.002 0.014 0.018 0.079 BSC 0.079 BSC 0.054 0.056 0.024 0.031
-XA M -YN B
0.25 (0.010) T 0.25 (0.010) T R 0.08 (0.003) T E H L
6 5 10 11
J C K -TSEATING PLANE
DIM A B C D E F G H J K L M N P R
G
F
1 20 16 15
D
NOTE 3 M
P TXY
0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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